1. Field of the Invention
The present invention relates to microprocessors and microcontrollers having an interrupt capability. More specifically, the present invention relates to structure and methods for enhancing the interrupt capability of such microprocessors and microcontrollers.
2. Description of Related Art
Polling of input/output service request flags uses a significant amount of microprocessor or microcontroller time. Polling also reduces system throughput, that is, the total useful information processed or communicated during a specified time period. Therefore, it is advantageous, in terms of increasing throughput, as well as reducing program complexity, if an input/output (I/O) device demands service directly from a microprocessor or a microcontroller. Interrupts provide this capability.
Essentially, an interrupt is a subroutine call initiated by external hardware. When an I/O device requires service, it may set an internal interrupt request flip-flop. Such a flip-flop has its output connected to an interrupt pin of the microprocessor or microcontroller. Thus, the flip-flop stores the I/O device's interrupt request until it is acknowledged by the microprocessor.
The interrupt requests are asynchronous; therefore, they may occur at any point in a program's execution. When an interrupt occurs, the execution of the current instruction is completed, the interrupt is acknowledged by the microprocessor, and control is transferred to a subroutine that services the interrupt (i.e., the service routine is "vectored to"). When the microprocessor or microcontroller responds to the interrupt, the interrupt request flip-flop is cleared by a signal directly from the microprocessor or by a device select pulse generated by the service subroutine. To resume program execution at the proper point when the I/O service subroutine is finished, the program counter is automatically saved before control is transferred to the service subroutine. The service subroutine saves the contents of any registers it uses on the stack, and restores the register's contents before returning. The contents of the program counter, the flag register, the accumulator, and the general purpose registers together represent the state of the microprocessor.
There are two types of interrupt inputs: non-maskable and maskable. When a logic signal is applied to a non-maskable interrupt input, the microprocessor is immediately interrupted. When a logic signal is applied to a maskable interrupt input, the microprocessor is interrupted only if that particular input is enabled. Maskable interrupts are enabled or disabled under program control. If disabled, an interrupt request is ignored by the microprocessor.
A non-maskable interrupt input can be masked externally by an interrupt mask signal from an output port. The mask bit from an output port may gate an interrupt signal. If the output instruction writes a 1 in the mask bit position, the interrupt may be enabled; if it writes a 0, it may be disabled.
In response to an interrupt, the following operations occur:
1. The microprocessor finishes processing the current instruction. PA1 2. An interrupt machine cycle is executed. During this cycle the program counter is saved and control is transferred to an appropriate memory location. PA1 3. The state of the microprocessor is saved. PA1 4. If more than one I/O device is associated with a location transferred to, the highest priority device requesting an interrupt is identified. PA1 5. A subroutine is executed which services the interrupting I/O device. This subroutine clears the interrupt service request flip-flop if it was not cleared in step two. PA1 6. The save state of the microprocessor is restored. PA1 7. Control is returned to the instruction that follows the interrupted instruction.
Each step above requires a certain amount of time. The combined times for a given microprocessor and external interrupt logic determine how quickly the microprocessor responds to an I/O device's request for service.
The time that elapses between the occurrence of the interrupt and the beginning of the execution of the interrupt-handling subroutine is the response time, that is, the sum of the times of steps one through four above. The difference between the total time that the microprocessor is interrupted and the actual execution time of the service subroutine is referred to as overhead. Interrupt structures with low overhead allow greater throughput.
Heretofore, in certain applications using commercially available microcontrollers such as the Intel 8051, there has been a need for a greater number of interrupts than are provided by those products. For example, the Intel 8051 has two external interrupts. In large, integrated systems it is not uncommon for designers to need or to otherwise be able to effectively use more than two interrupts. Heretofore, there has been no inexpensive, easily implemented way to augment or otherwise enhance the interrupt capability of generally available microprocessors and microcontrollers. This lack has been a shortcoming and deficiency of the prior art.